Research on Calibration method for TIADC based on multi-channel all-phase FFT frequency discriminator
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摘要:
针对激光三维成像雷达、高速光信号采集等光学系统中时间交织模数转换器（Time-Interleaved Analog to Digital Converter, TIADC）各通道间存在的失调、增益与采样时间失配误差引入杂散分量与非线性失真，导致激光回波信号采样精度降低、测距与解调性能下降的问题。本文提出一种基于多通道全相位快速傅里叶变换（Fast Fourier Transform，FFT）频率判别器的TIADC全数字校准算法，设计多通道全相位FFT频率判别器，利用全相位FFT的相位不变性与多通道采样的相位关联性，实现输入信号频率的高精度估计与区间判别，解决传统算法高频区间失效问题；最终结合LMS自适应滤波架构，完成偏置、增益、采样时间三类失配误差的同步联合校准。基于MATLAB与FPGA搭建采样率2 GHz的4通道TIADC实验平台开展验证，实验结果表明，所提频率判别器在−5 dB极低信噪比下仍保持96.7%的频率区间判别正确率；经所提算法校准后，系统无杂散动态范围从未校准的19.8 dB提升至81.2 dB，信噪失真比提升至73.8 dB。该算法无需专用校准信号，在低信噪比场景下具备优异的校准性能，可为激光雷达、高速光通信等光学领域的高速高精度采样系统提供核心技术支撑。
Abstract:Time-interleaved analog-to-digital converters (TIADCs) overcome the sampling rate bottleneck of monolithic ADCs and enable ultra-high-speed broadband acquisition of optical signals in applications such as laser 3D imaging lidar and high-speed optical communication systems. However, their practical performance is fundamentally limited by inter-channel mismatches in offset, gain, and sampling timing, which introduce pronounced spurious components and nonlinear distortion. Such errors directly degrade the sampling accuracy of laser echo signals and impair system ranging and demodulation performance. To address this issue, this paper proposes an all-digital TIADC calibration algorithm based on a multi-channel all-phase fast Fourier transform (FFT) frequency discriminator. A two-stage low-pass filtering and interpolation reconstruction architecture is devised, paired with the multi-channel all-phase FFT frequency discriminator. By exploiting the phase invariance property of all-phase FFT and the phase correlation of multi-channel sampling, the proposed method achieves high-precision frequency estimation and interval discrimination of input signals, which eliminates the inherent high-frequency performance deterioration of traditional algorithms. Integrated with a least mean square (LMS) adaptive filtering framework, the algorithm realizes synchronous joint calibration of offset, gain, and sampling timing mismatch errors. A 4-channel TIADC experimental platform with a total sampling rate of 2 GHz is constructed based on MATLAB and FPGA for performance verification. Experimental results demonstrate that the proposed frequency discriminator maintains a frequency interval discrimination accuracy of 96.7% even at an extremely low signal-to-noise ratio (SNR) of −5 dB. After calibration, the spurious-free dynamic range (SFDR) of the system is improved from 19.8 dB to 81.2 dB, and the signal-to-noise and distortion ratio (SNDR) reaches 73.8 dB. The proposed algorithm operates without dedicated calibration signals and exhibits outstanding calibration performance under low-SNR conditions, providing core technical support for high-speed, high-precision sampling systems in optical fields including lidar and high-speed optical communication.
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Key words:
- TIADC /
- channel mismatch calibration /
- all-phase FFT /
- frequency discriminator
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图 1 M通道TIADC并行交替采样原理图
Figure 1. Schematic Diagram of Parallel Time-Interleaved Sampling for M-Channel TIADC
图 12 实测校准前后时域波形对比图
Figure 12. Comparison of measured time-domain waveforms before and after calibration on hardware platform
图 13 硬件实测校准前后频谱对比
Figure 13. Comparison of measured frequency spectrums before and after calibration on hardware platform
图 14 硬件实时校准误差收敛曲线
Figure 14. Error Convergence Curve for Real-Time Hardware Calibration
表 1 不同频率输入信号调整规则表
Table 1. Adjustment Rules for Input Signals at Different Frequencies
信号频率范围 第一次插值调整 第二次插值调整 $ [0,{f}_{ch}/2] $ 不变 不变 $ [{f}_{ch}/2,{f}_{ch}] $ 隔值取反 不变 $ [{f}_{ch},3{f}_{ch}/2] $ 隔值取反 隔值取反 $ [3{f}_{ch}/2,2{f}_{ch}] $ 不变 隔值取反 
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表 2 TIADC系统实验参数配置
Table 2. Experimental Parameter Configuration of the TIADC System
参数名称 参数取值 系统总采样率$ {F}_{s} $ 2 GHz 单通道ADC采样率$ {f}_{ch} $ 500 MHz ADC分辨率 14 bit 采样点数 20000 全相位FFT点数 1024 输入频率 100 MHz
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表 3 通道失配误差配置表
Table 3. Configuration of Channel Mismatch Errors
通道号 偏置误差
（LSB）增益失配
(相对值)采样时间失配
（$ ps $）1（参考） 0 0 0 2 3.5 0.025 9.2 3 −4.8 −0.022 −7.5 4 2.9 0.018 6.7
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表 4 不同信噪比下频率判别器性能对比
Table 4. Comparison of Frequency Discriminator Performance under Different SNRs
信噪比 过零点检测 频率判别器 −5 dB 3.2% 96.7% 0 dB 8.7% 98.4% 5 dB 12.8% 99.1% 10 dB 31.6% 99.6% 15 dB 67.5% 100% 20 dB 92.3% 100% 25 dB 96.1% 100%
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表 5 不同输入信号频率下频率判别器性能对比
Table 5. Performance Comparison of Frequency Discriminators at Different Input Frequencies
输入信号频率 所属区间 过零点检测 频率判别器 100 MHz $ [0,{f}_{ch}/2] $ 92.3% 100% 200 MHz $ [0,{f}_{ch}/2] $ 91.7% 100% 300 MHz $ [{f}_{ch}/2,{f}_{ch}] $ 90.5% 100% 400 MHz $ [{f}_{ch}/2,{f}_{ch}] $ 89.2% 99.1% 600 MHz $ [{f}_{ch},3{f}_{ch}/2] $ 87.6% 98.4% 700 MHz $ [{f}_{ch},3{f}_{ch}/2] $ 86.3% 100% 900 MHz $ [3{f}_{ch}/2,2{f}_{ch}] $ 85.1% 100% 950 MHz $ [3{f}_{ch}/2,2{f}_{ch}] $ 84.3% 100%
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表 6 本文算法校准性能验证结果
Table 6. Verification Results of Calibration Performance for the Proposed Algorithm
输入信号频率 性能指标 未校准 文献[19] 本文方法 100 MHz SFDR 19.8 62.3 81.2 SNDR 18.5 60.1 73.8 300 MHz SFDR 21.2 58.7 80.5 SNDR 19.7 56.9 73.2 600 MHz SFDR 20.5 42.3 79.3 SNDR 19.2 40.1 72.1 900 MHz SFDR 20.9 38.7 78.4 SNDR 19.5 36.8 71.5
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表 7 不同信噪比下联合校准性能对比
Table 7. Performance Comparison of Joint Calibration under Different SNRs
信噪比（dB） 未校准 文献[19] 本文方法 0 18.2 35.7 72.5 5 19.5 42.3 75.3 10 20.1 51.2 77.8 15 20.7 58.7 79.6 20 21.2 62.3 80.5 25 21.5 64.1 81.2
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表 8 FPGA校准算法核心模块资源消耗统计
Table 8. Resource Utilization of Core Modules of the FPGA Calibration Algorithm
资源类型 实际占用数量 器件总可用数量 资源占用比 查找表（LUT） 12864 203800 6.3% 触发器（FF） 18792 407600 4.6% 块存储器（BRAM） 16 445 3.6% DSP运算单元 28 840 3.3%
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