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Design and application of CCD/EMCCD photoelectronic parameter test system

SHEN Ji VIACHESLAV V. Zabudsky CHANG Wei-jing NA Qi-yue JIAN Yun-fei OLEG V. Rikhalsky OLEKSANDR G. Golenkov VOLODYMYR P. Reva

沈吉, VIACHESLAV V. Zabudsky, 常维静, 那启跃, 简云飞, OLEG V. Rikhalsky, OLEKSANDR G. Golenkov, VOLODYMYR P. Reva. CCD/EMCCD光电参数测试系统的设计与应用[J]. 中国光学(中英文), 2024, 17(3): 693-703. doi: 10.37188/CO.EN-2023-0016
引用本文: 沈吉, VIACHESLAV V. Zabudsky, 常维静, 那启跃, 简云飞, OLEG V. Rikhalsky, OLEKSANDR G. Golenkov, VOLODYMYR P. Reva. CCD/EMCCD光电参数测试系统的设计与应用[J]. 中国光学(中英文), 2024, 17(3): 693-703. doi: 10.37188/CO.EN-2023-0016
SHEN Ji, VIACHESLAV V. Zabudsky, CHANG Wei-jing, NA Qi-yue, JIAN Yun-fei, OLEG V. Rikhalsky, OLEKSANDR G. Golenkov, VOLODYMYR P. Reva. Design and application of CCD/EMCCD photoelectronic parameter test system[J]. Chinese Optics, 2024, 17(3): 693-703. doi: 10.37188/CO.EN-2023-0016
Citation: SHEN Ji, VIACHESLAV V. Zabudsky, CHANG Wei-jing, NA Qi-yue, JIAN Yun-fei, OLEG V. Rikhalsky, OLEKSANDR G. Golenkov, VOLODYMYR P. Reva. Design and application of CCD/EMCCD photoelectronic parameter test system[J]. Chinese Optics, 2024, 17(3): 693-703. doi: 10.37188/CO.EN-2023-0016

CCD/EMCCD光电参数测试系统的设计与应用

详细信息
  • 中图分类号: TN205

Design and application of CCD/EMCCD photoelectronic parameter test system

doi: 10.37188/CO.EN-2023-0016
Funds: Supported by National Science and Technology Major Project from Minster of Science and Technology, China (No. 2018AAA0103100)
More Information
    Author Bio:

    Shen Ji (1988—), male, born in Haimen, Jiangsu Procince, Master degree, Senior Engineer. He received his master degree form Nanjing University of Science and Technology, Optical Engineering in 2014. He is mainly engaged in research of photoelectric device, module and testing. E-mail: njustshenji@126.com

    Corresponding author: njustshenji@126.com
  • 摘要:

    本文开发了一种用于测量CCD和EMCCD(电子倍增CCD)芯片光电参数的测试系统。该测试系统通过自动模式或手动模式间的切换,测量器件的暗电流、读出放大器的响应度、电荷转移效率、电荷容量和其他参数。该测试系统可以针对不同规格和结构的CCD/EMCCD器件,实现CCD晶圆或封装好的成品的参数测试,实现576×288、640×512、768×576、1024×1024、1280×1024 CCD/EMCCD的测试和筛选。

     

  • Figure 1.  Block diagram of the entire test system

    Figure 2.  The block diagram of the direct and pulse voltage source unit

    Figure 3.  Block diagram of the FPGA board

    Figure 4.  Block diagram of the device (outlined by a dashed line) implemented in FPGA

    Figure 5.  Amplification of DACs output voltages

    Figure 6.  High voltage amplifier circuit

    Figure 7.  Schematic diagram of the experimental driver on the base of GaN HEMT

    Figure 8.  Driver’s power consumption and temperature at different output voltages and loads

    Figure 9.  Flow chart for measuring maximum output voltage, charge capacity, and output amplifier responsivity

    Figure 10.  Measuring results of test system. Volt-charge responsivity for normal and gain modes, average dark signal, and dependence of gain on R02HV voltage were measured

    Table  1.   Parameters of 16 DC channels

    Channel
    quantity
    Setting range/
    V
    Total relative
    error
    Noise,
    mV/300 kHz
    1 −5···+10 typical: ±0.1%;
    maximal: ±0.5%
    from Vmax
    <0.15
    3 0···+15 < 0.15
    4 −5···+15 < 0. 20
    4 0···+25 < 0.40
    4 0···35 < 0.70
    下载: 导出CSV

    Table  2.   Parameters of 16 AC channels

    Channel quantity Setting range/ V Wave front/ ns Load (each channel)
    3 HL, LL: –5...+10 120..200 up to 24 nF
    4 HL: –5...+10 or 0...+15
    LL: –5...+10 or 0...+15
    < 15 220 pF
    1 HL: 0...+15
    LL: 0...+15
    < 15 220 pF
    6 HL: +5
    LL: 0
    < 5 150 pF
    1 HL: –5...+ 15;
    LL, ML: –5...+10
    (three level signal)
    120..200 up to 24 nF
    1 HL: –5...+45
    LL: –5...+ 45
    (square or sine wave)
    20 100 pF
    下载: 导出CSV

    Table  3.   Electrical parameters of EMCCD matrices measured by the test system

    NoParameterRange
    1Resistances between the pairs of
    chip contact pads
    2Average Dark Signal> 1 e/pixel/s
    3Dark Signal Non-uniformity (DSNU)
    4Multiplication Gain1~1000
    5Peak Output Voltage (POV)< 1 V
    6Output Amplifier Responsivity (OAR)μV/e-
    7Register Charge Handling
    8Electric Charge Transfer Efficiency (CTE)≤ 0.99995
    下载: 导出CSV

    Table  4.   Measurements example of test system

    1. POV nm, norm mode (max) = 0.177 V;
    2. SC is (saturation charge) = 132151 e`/pixel;
    3. POV hgm, high gain mode (max) = 1.782 V;
    4. CHCgr, Charge Handling Capability of gain
    register = 1280481 e`/pixel;
    5. White column defects = 3
    6. Dark column defects quantity = 18
    7. Average Dark Signal (U) = 0.002939 V/pixel/s
    8. Average Dark Signal (e`) = 2396 e`/pixel/s
    9. OAR (output amplifier responsivity) = 1.416 uV/e`
    (NM: 1.226 uV/e`)
    10. Dark signal non-uniformity (DSNU) (rms) = 67.334 %
    11. Charge transfer efficiency (CTE) = 99.908 %
    下载: 导出CSV
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出版历程
  • 收稿日期:  2023-07-04
  • 修回日期:  2023-08-11
  • 录用日期:  2023-08-28
  • 网络出版日期:  2023-09-12

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